Intel calls for end to inflated nanometers
During the recent Manufacturing Day events 2017 Intel the mouth of Mark Bohr (Mark Bohr), honored senior researcher and Director of process architecture and integration Intel, suggested the industry to clarify the definition of technological standards.
Before the transition to each subsequent step led to a doubling of the degree of integration or density of the layout: on the same square crystal fit twice as many transistors. For example, it was during the transition from 90 nm to 64 nm and then to 45 nm and 32 nm. Recently, however, according to Bor, this is due to the growing complexity of further reducing the size — some companies have abandoned this rule, using all the lower numbers to denote the norms in minimal, if not absent increase the density of the layout. The result of the declared values do not show the real capabilities of the process and his position on the chart corresponding to Moore’s law.
To be clear, Intel offers to determine the capabilities of process technology on a formula which includes the size of the model blocks is the simplest NAND cell and a more complex trigger — and the number of transistors in them. The relative prevalence of simple and more complex elements are reflected in the weights.
If every manufacturer will publish the value obtained by this formula for a particular process technology, will be able to compare different processes from one manufacturer and from different manufacturers. Companies involved in reverse engineering will be able to easily verify the declared value.
Another common building block for chips are SRAM cells. Their presence can significantly influence the degree of integration, defined as the number of transistors per unit chip area. Given that in different circuits, the ratio of the number of SRAM cells and logic blocks are significantly different, the cell size of SRAM is requested to report separately.