Board BittWare XUPP3R with 16-nanometer FPGA Xilinx Virtex UltraScale+ became the basis for the development of Enyx, releasing the CPU from processing packets of 25G Ethernet
At a conference on supercomputers SC16 company Enyx presented the expansion card to the PCIe slot, releasing the CPU from handling TCP packets and UDP when connecting 25G Ethernet. The heart of the model served as a Board BittWare XUPP3R with 16-nanometer FPGA Xilinx Virtex UltraScale+ VU9P, so it would be correct to say that Enyx offers IP cores for the implementation of this functionality in FPGA and SoC.
The manufacturer stresses that the IP core Enyx nxTCP and nxUDP with integrated MAC interface fully compliant with IEEE 802.3, supporting protocols ARP, IPv4, ICMP, IGMP and TCP/UDP. Allegedly, the support of 25G Ethernet in these IP cores not only meet the growing demand for bandwidth network equipment for data centers, but also opens the way for the subsequent implementations of 50G and 100G. Release the CPU from packet processing is a key condition for ensuring a stable high bandwidth and computing performance.