At the stage of technological standards 4 nm Samsung plans to use the architecture of the transistors MBCFET
Samsung at the annual event Samsung Forum Foundry has told about plans of development of new norms of technological process. Samsung plans include the development of technological standards 8, 7, 6, 5 and 4 nm. In addition, the planned development standards 18 nm technology FD-SOI.
More specifically, the South Korean manufacturer plans include development of the following processes:
- 8LPP (8 nm Low Power Plus): this is the final step before proceeding to the lithography in the hard ultraviolet range (EUV). Being a development of 10-nanometer technology 10LPP, it will increase the density of the layout and performance.
- 7LPP (7 nm Low Power Plus): this is the first EUV process technology. The source of EUV radiation with a power of 250 W required for serial production, developed jointly by Samsung and ASML.
- 6LPP (6 nm Low Power Plus): will contribute to further increasing the density and reducing energy consumption through the use of proprietary scaling technology Samsung Smart Scaling.
- 5LPP (5 nm Low Power Plus): the last stage that will use FinFET transistors.
- 4LPP (4 nm Low Power Plus): in this phase, Samsung plans to move to a new architecture of transistors, called MBCFET (Multi Bridge Channel FET). A feature of the implementation of the MBCFET is a proprietary technology Samsung GAAFET (Gate All Around FET), which uses nanomaterials.
- FD-SOI (Fully Depleted – Silicon on Insulator): technology process 18FDS will replace the current 28FDS. It will allow to integrate in one crystal logic and radio frequency circuits and the memory eMRAM (embedded Magnetic Random Access Memory).
The terms of the plan, the source does not name.
Source: Samsung Electronics